1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for forming features in semiconductor manufacturing.
2. Background Art
Today, our society is heavily dependent on high-tech electronic devices for everyday activity. Integrated circuits are the components that give life to our electronic devices. Integrated circuits are found in widespread use throughout our country, in appliances, in televisions and personal computers, and even in automobiles. Additionally, modern manufacturing and production facilities are becoming increasingly dependent on the use of machines controlled by integrated circuits for operational and production efficiencies. Indeed, in many ways, our everyday life could not function as it does without integrated circuits. These integrated circuits are manufactured in huge quantities in our country and abroad. Improved integrated circuit manufacturing processes have led to drastic price reductions and performance enhancements for these devices.
The traditional integrated circuit fabrication process is a series of steps by which a geometric pattern or set of geometric patterns are transformed into an operational integrated circuit. An integrated circuit consists of superimposed layers of conducting, insulating, and device-forming materials. By arranging predetermined geometric shapes in each of these layers, an integrated circuit that performs the desired function may be constructed. The overall fabrication process consists of the patterning of a particular sequence of successive layers. The patterning process used to fabricate integrated circuits is typically performed using lithography followed by a variety of subtractive (etch) and additive (deposition) processes.
Photolithography, a type of lithographic process, is used in the manufacturing of semiconductor devices, integrated optics, and photomasks. The process typically involves the following steps: applying a layer of a material (known as a photoresist, or resist) that will react when exposed to actinic or activating energy; exposing portions of the photoresist to actinic energy such as light or other ionizing radiation, i.e., ultraviolet, electron beams, X-rays, etc., thereby changing the solubility of portions of the resist; and developing the resist by washing it with a basic developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the layer.
As the need for higher and higher levels of integration has arisen in the industry, the need for a larger number of patterns, lines, and spaces in a given area has increased dramatically. In response, the scaling of lithographic features has been an essential aspect of enhancing the performance and density of semiconductor devices.
Previously, a hybrid resist was disclosed which possessed both a negative tone and a positive tone response as explained in the related applications listed above. Spaces can be formed in hybrid resist that are smaller than can be formed in normal resist. For example, 0.15 .mu.m spaces can be formed in hybrid resist using lithography tools that are normally limited to 0.30 .mu.m resolution. This is possible because hybrid resist, when exposed and developed, forms a space in the region that corresponds to the transition from light to dark at the edge of an aerial image. That is, the portion of the resist exposed to some predetermined range of radiation intensity less than full intensity but more than zero intensity will develop away to become a space.
The size of the space is dependent upon several factors. In particular, the size of the space is a function of the sharpness of the exposure profile and the resist chemistry. Because the space width formed in hybrid resist is a function of the exposure profile, the width of spaces can be tightly controlled. In particular, the space width is generally unchanging as the exposure dose and the reticle image size are changed, allowing for very precise image control for a set space width within each chip.
Unfortunately, the same features that allow hybrid resist to be used to print space widths with precise control limits the ability to create spaces with different widths. In particular, as mentioned above, the exposure profile and hence the space width is generally a function of the numerical aperture (NA) of the lithography tool. Generally, it is impractical to change the NA of a lithography tool between fabrication steps. Because the NA cannot be changed, it is not possible using current methods to form hybrid spaces with different widths. Instead, once the NA and hybrid resist chemistry is selected, the space width is set and varied space widths cannot be easily produced in the same resist layer.
Thus, it would be an improvement in fabrication technology to provide a method for forming spaces in the resist with widths different than the hybrid resist space.